Job Description: Role and Responsibilities
As an Engineer responsible for CPU Random Tools for stress verification, you will work with a sophisticated Random Instruction Sequences (RIS) tool. With a combination of techniques, the tool verifies the functionality of our CPU cores, designed in Austin (US), Cambridge (UK), Chandler (US) or Sophia Antipolis (FR). The existing team ensures the addition of new features of the architecture, its customization to specific CPU cores, and provides support.
You will be based at Arm’s Bangalore design center in India.
- As a Verification Engineer, your role will include tool development from development to deployment, and will be responsible for:
- Understanding the intricacies of CPU micro-architecture and determining how to push the boundaries of testing;
- Architect and develop solutions to improve the generation of stimuli to create programs to promote our next generation CPUs;
- Tool implementation and support, from the early stages of CPU development to product maturity.
- Problem with ownership and ability to work from abstract requirements
- Good communication and presentation skills
- Self-motivated and ready to take on additional responsibilities
- Quick learner with a strong desire to learn and develop new skills
Qualifications and Experience
- B.Tech/BS or MTech/MS in Computer/Electronics Engineering or Computer Science from a reputed institute
- 3-6 years of solid proven experience with significant project contribution
- You hold experience in software design, and must be comfortable working with low-level hardware
- You have a good solid understanding of programming languages, such as C and Python
- You know about CPU architecture and micro-architecture concepts
- You understand assembly language (ASM)
- You have strong interpersonal skills and the ability to work well as part of a team with a willingness to tackle a variety of technical challenges.
- Fundamentals of Processor Architecture.
- Fundamentals of ARM Architecture.
- Familiarity with EDA tools and Hardware Design Verification.